At the Intel Developer Forum in Beijing, Intel executives today detailed more than 20 new products, technology innovations and industry initiatives -- many of them industry firsts -- aimed at making the World Wide Web, computers and consumer electronics devices much more responsive, friendlier and secure. Under the backdrop of Intel’s leadership in 45nm Hi-k metal gate silicon technology and how it will ignite new innovation and growth opportunities, Intel executives disclosed new performance details for its next-generation “Penryn” processor family. The company also unveiled two product roadmaps for Intel architecture (IA)-based System on Chip (SOC) and business uses. Intel SVP Pat Gelsinger provided performance indicators for Intel's upcoming Penryn family of processors. For high-performance computing (HPC) and workstation systems, Gelsinger said to expect gains up to an estimated 45 percent for bandwidth intensive applications; and a 25 percent increase for servers using Java. These indicators were derived from pre-production 45nm Hi-k Intel Xeon processors with 1600 MHz front side bus for workstation and HPC, and a 1333 MHz front side bus for servers versus today’s quad-core Intel Xeon X5355 processors. Justin R. Rattner, Intel’s chief technology officer said that Intel has begun planning products based on a highly parallel, IA-based programmable architecture codenamed “Larrabee.” It will be easily programmable using many existing software tools, and designed to scale to trillions of floating point operations per second (Teraflops) of performance. The Larrabee architecture will include enhancements to accelerate applications such as scientific computing, recognition, mining, synthesis, visualization, financial analytics and health applications. The company also has plans for Intel QuickAssist Technology – a comprehensive initiative to optimize the use of accelerators in servers. Accelerators increase the performance of a single function, like security encryption or financial computation, while reducing power consumption. This initiative includes support for acceleration using IA-based multi-core processors and third party accelerators working together in Intel-based servers, and developing new integrated accelerators inside the IA-based processor itself. Gelsinger unveiled “Tolapai” plans, the first in what will be a family of enterprise-class "system-on-chip" (SoC) products that integrate several key system components into a single Intel architecture-based processor. The 2008 Tolapai product is expected to reduce the chip sizes by up to 45 percent and power consumption by approximately 20 percent compared to a standard four-chip design, while improving throughput performance and processor efficiency. Tolapai will include the new Intel QuickAssist Integrated Accelerator technology. Gelsinger also outlined product plans, including one for Intel’s high-end multi-processor servers (codenamed “Caneland”). The quad- and dual-core Intel Xeon processor 7300 series will arrive in the third quarter in 80- and 50-watt versions for blades. The new servers will complete the company’s transition to its Intel Core microarchitecture for Xeon processors. Sun Microsystems demonstrated its Solaris operating system running on an Intel Xeon 5100 series processor based system using Intel Dynamic Power technology, a new capability focused on reducing the power required for a memory subsystem. Finally, Microsoft demonstrated Windows Server code name "Longhorn" and two complementary technologies: Windows Server Core, and its new hypervisor-based virtualization solution, Windows Server virtualization, running on the Intel quad-core Xeon processors. The integrated platform combination, demonstrates running up to 8 core virtual machines, with "hot add" features, delivering increased efficiency and uptime for IT managers. In his opening address, Rattner reiterated the company’s goals for processor performance and energy efficiency noting that Intel will be able to drive down power consumption by a factor of 10 for the ultra mobile computing segment by 2010. Intel will also create future processors at Teraflops speeds, and Rattner urged the industry to work together to take advantage of this raw processing power. The next stage of Intel’s tera-scale research will be around “stacked” memory on top of the 80-core research chip Intel demonstrated earlier this year.