Tensilica has announced that AppliedMicro has selected Tensilica's Xtensa LX dataplane processors (DPUs) for an upcoming high-throughput communications chip design project.

"We selected Tensilica's DPUs because of their remarkable ability to be customized with high-bandwidth, efficient interfaces, such as FIFO-like queues, to quickly stream data into and out of the processor," stated Sean Campeau, AppliedMicro's senior manager of engineering. "These high-speed connections bypass the main system bus altogether, allowing us to implement functions in the processor that previously could only meet our performance targets by being implemented in RTL (register transfer level) logic. Implementing these functions in a processor speeds our design effort considerably and gives us a much more flexible solution."

"AppliedMicro's project is typical of high performance dataplane signal processing designs that can take advantage of our customizable dataplane processor (DPU) and specialized I/Os," stated Steve Roddy, Tensilica's vice president of marketing and business development. "In the dataplane, our customers often need data throughput and computational performance that can't be achieved using traditional processors. With our unique and patented process of automated customization of dataplane processors, application-specific I/Os can be rapidly added to a processor core to meet any desired I/O bandwidth requirement."