ENGINEERING

SANTA CLARA, CA -- PACT Corporation, a leader in the development of reconfigurable parallel coprocessor cores and solutions, today announced the implementation of a new set of design rules and processes for the company's eXtreme Processor Platform (XPP(TM)). XPP is deployed as a licensable IP (Intellectual Property) core for incorporation within SOC or DSP designs used in markets such as 2.5G+ base stations, mobile telephones and other devices requiring fully reconfigurable, massively parallel processing capabilities with minimum power requirements and maximum scalability. XPP utilizes a massively parallel 'virtual ASIC' array of PAEs (Processing Array Elements, made up of individual Arithmetic Logic Units) that can be reconfigured on the fly, erased and rebuilt with virtually zero latency. These virtual ASICs can also execute, be modified, or erased fully in parallel of one another, or even with data interchange, across the array -- all the while being fully controlled via a unique configuration manager that insulates timing and data-dependency issues from the programmer or designer. The core is tailored to meet the exponentially growing demands for bandwidth and performance: benchmarks on the company's XPU-128 sample chip have proven it to be the world's fastest 32-bit design. The core enables efficient reconfiguration strategies, which can be performed in parallel for the processing of data to achieve the highest possible application performance -- equal to 50,000 MIPS or the equivalent of 80 Pentium(R) 4 chips running in parallel at 1.3 GHz, based on the initial 100 MHz clock speed of the core. Using the LSI Logic (Milpitas, CA) .18 geometry ASIC Library has enabled PACT to increase the clock speed of the core by 33% to 150 MHz+, while simultaneously reducing the die size requirements for each individual PAE in the XPP core. The power consumption for typical DSP algorithms running on XPP is between 0.15W and 1.5W at the new clock frequency of 150 MHz. Using less than 10% of the power draw of leading DSP designs, XPP enables new benchmarks of flexibility and performance in silicon/software design and implementation. Using the .18 technology, a complete PAE structure including configuration management and networking is now reduced to the following unprecedented size at a 150 MHz+ clock frequency: 32-bit ALU/PAE: 1mm(square) 24-bit ALU/PAE: 0.8mm(square) To put this into perspective -- an array of 80, 24-bit PAEs especially adapted to wireless applications such as CDMA, Software Defined Radio, 802.11b and others can now achieve a performance of 12,000 24-bit MegaMACs / sec. or 24,000 12-bit MegaMACs / sec., with a total array size of 64mm(square). For implementation as a high-performance workstation coprocessor using 128, 32-bit PAEs now require an array size of 128mm(square), delivering a performance of up to 76,800 32-bit MIPS or 307,200 8-bit MIPS. PACT delivers a full suite of IP to its licensees, including a complete toolset for programming and debugging XPP cores (including several High-Level languages such as NML (Native Mapping Language) and a beta version of the upcoming C compiler for XPP). PACT provides extensive support for the optimization and integration of its IP cores into the customer's project as well as algorithm development support. The company is currently in license negotiations with leading DSP and CPU vendors worldwide regarding XPP. "Through PACT's patented technolgoy and innovation, reconfigurable processors have now reached the level where they outperform ASIC and FPGA in both development time and cost," said Martin Vorbach, CTO of PACT. "The use of these new libraries has allowed PACT to significantly lower power dissipation and unit cost to the point where we now significantly beat competing technologies." For further information visit www.pactcorp.com