SCIENCE
NEC Launches Internet-Based Collaborative Design Environment for Gate Arrays
SANTA CLARA, CA -- NEC Electronics today
announced it has launched the NEC Gate Array Design Center Internet site, a
new online collaborative design environment to ease and accelerate the gate
array integrated circuit (IC) design process. This dedicated site provides NEC
customers with the tools and support needed to quickly and easily take
advantage of the cost and performance benefits offered by gate arrays. The
easy-to-use site includes real-time pricing, turnaround time and packaging
information to speed the evaluation process and also facilitates quick product
development through online training, design tutorials and technical and sales
support. Gate array designers will also have access to popular design tools
through NEC's OpenCAD(R) design environment. Using the NEC Gate Array Design
Center Internet site, NEC expects that designers can improve their
productivity and speed their time to market.
"NEC is committed to enabling Internet-based design, and we are proud of
the extensive online support and training programs we've developed to help our
gate array customers cut costs and increase productivity," said Bart Ladd,
assistant general manager of NEC Electronics' LSI Strategic Business Unit.
"While FPGAs and cell-based ASICs are growing in popularity, gate arrays offer
many cost and performance benefits for mid-range computing, networking and
consumer IC designers. According to Dataquest, gate arrays represent a
$2.4 billion market opportunity through 2002, and with our new collaborative
design environment, we've made it even easier for designers to choose gate
arrays for their IC designs."
Design Environment Features
NEC's Internet-based collaborative design environment includes many
user-friendly features that will aid designers in the design evaluation
process, including an online calculator, automatic price estimator and
detailed product information on the available gate array families -- the
CMOS-9HD and the CMOS-N5 (more on NEC's gate array families below). The
unique online calculator enables designers to input the amount of user-defined
logic, major macros and package options to easily compare the cost of gate
arrays to other IC solutions. The site also provides for online delivery of
all documents and contracts to facilitate easy project set-up. Once a design
is in progress, the NEC Gate Array Design Center Internet site enables
designers to track their engineering samples and monitor progress throughout
the manufacturing process. NEC Systems, an IT consulting and solutions
provider and an affiliate of NEC Corporation, designed the site's architecture
to deliver an intuitive user interface and easy access to the site's key
features.
Through a partnership with GDA Technologies, a supplier of electronics
design services, NEC's site will provide customers with front-end support,
ASIC back-end services and sign-off services. In addition, GDA will provide
technical support for customers using the NEC OpenCAD design environment,
which includes popular third-party EDA tools as well as NEC proprietary front-
end, back-end and verification design tools. Where additional assistance is
needed, GDA will provide front-end design, Design For Test (DFT) services,
FPGA-to-ASIC conversion, board-level validation and system qualification
services.
NEC Electronics is additionally working with Future Electronics as its
distributor for products developed using NEC's Gate Array Design Center
Internet site. "Future and NEC Electronics have a long, successful history of
working together to promote products," said Jeffrey Skill, vice president,
Technical Solutions Management Group, Future Electronics. "We believe that
NEC's technical expertise combined with our large number of skilled technical
solutions managers is a winning combination that can provide tremendous value
in gate array design, development and support."
Gate Array Advantages
Gate arrays consist of sea-of-gates fixed arrays that are prefabricated on
wafers and offer several cost and performance benefits over programmable logic
or cell-based ASICs. As with FPGAs, all the prefabricated gate arrays are the
same so they can be made in large volumes to keep costs down. Unlike FPGAs,
gate arrays don't have programmable interconnections to take up a lot of
silicon real estate and add signal delay, reducing the speed of the IC. With
gate arrays, completing the final metalization step in the fabrication process
interconnects the gates. This step takes much less time, and is much less
expensive, than developing a cell-based ASIC. With the short turnaround time,
designers can easily spin multiple versions to perfect a design, provide
inexpensive upgrades or modify functionality. "With a 22 percent market share
in North America, NEC Electronics is the recognized leader in the gate array
market," said Bryan Lewis, chief analyst at Gartner Group's Dataquest. As the
leader in gate arrays, NEC delivers the above benefits in a variety of package
types, gate counts and speeds. These choices are divided into NEC's CMOS-9HD
family and CMOS-N5 family.
The high-density, high-speed CMOS-9HD family offers a cost-effective
alternative to both high-end FPGAs and low-end cell-based ASICs. Usable gate
counts in the CMOS-9HD family range from 53K to 1.5M gates. These gate arrays
utilize a 0.35 um, three- or four-layer-metal process for efficient use of
silicon at 15K gates/mm2. The high-speed devices operate at clock speeds up
to 100 MHz and offer low power consumption by using a 3.3-volt supply with
5-volt compatibility. The CMOS-9HD family offers macros such as RAM, ROM,
peripherals and PLLs.
With usable gate counts ranging from 2K to 86K gates, the NEC CMOS-N5
family offers ideal replacements for moderate-capacity FPGAs. Unlike FPGAs,
these gate arrays can operate at up to 60 MHz on a single 5-volt supply for
power conservation and compatibility with other low-voltage chips. Using a
mature 0.5 um, 2-layer-metal process, CMOS-N5 gate arrays are much more cost
effective than FPGAs or cell-based ASICs. The CMOS-N5 family offers macro
choices including single- and dual-port RAMs and a programmable DMA controller
to UARTs. The family includes several types of flat-pack packages with pin
counts as high as 304 pins.
For more information visit www.necgatearray.com