SYSTEMS

CAMPBELL, CA -- Tera Systems announced today that LSI Logic (NYSE:LSI) has signed a multi-year agreement to outfit its design centers with TeraFormu, Tera Systems' family of front-end RTL (register transfer-level) design planning, analysis, and prototyping tools for complex, system-on-chip (SoC) design. LSI Logic will use the TeraForm tools in its design centers as part of the FlexStream(R) design flow for ASICs and SoCs. The TeraForm tools are being used on customer designs prior to synthesis to identify potential timing and design closure issues early in the design cycle, leading to better predictability and shorter time-to-market. "Our customers demand that we deliver increasingly complex, high performance designs in less time," said Dan Deisz, a senior director in Worldwide Customer Engineering at LSI Logic. "With TeraForm, we can analyze customer designs early in the design process at the RTL, and identify design architecture issues, layout bottlenecks, and timing problems up front, thereby saving substantial time and resources." "Extreme Networks is engaged in a fiercely competitive industry and can only retain its leadership position in the networking marketplace by being the first to market with the most advanced ASIC-based products," said Dan Cimino, director of ASIC development at Extreme Networks. "The complexity of the latest generation of ASICs is beyond what we could have achieved using previous generation tools. LSI Logic's analysis of our RTL code using TeraForm is a critical step in Extreme's efforts to complete this advanced generation of networking products." LSI Logic Outfits Design Centers with TeraForm ASIC customer engineers in the LSI Logic design centers worldwide are gaining access to TeraForm's pre-emptive diagnosis and "what-if" analysis capabilities. These analyses identify ASIC and SoC design problems, such as routing congestion and critical path timing violations, that frequently occur late in the synthesis and physical layout processes when they are most difficult to fix. TeraForm enables engineers to evaluate the quality of RTL blocks and gain early visibility into the impact of the code on chip architecture definition. LSI Logic design center engineers using TeraForm can analyze customers' RTL code and, if necessary, give customers prescriptive advisories to correct for problems prior to back-end implementation. The benefits to LSI Logic's customers are faster, more predictable design turnaround and minimal iterations between logical and physical design phases. "LSI logic is a world leader in communications and networking ASICs and SoCs and engages in hundreds of new designs each year," said Mark Miller, vice president of Marketing and Business Development for Tera Systems. "Design center engineers need to come up to speed on the unique architecture of each customers design in a matter of a few weeks to meet demanding schedule and performance requirements. TeraForm gives LSI Logic's engineers the foresight they need to locate hard-to-find RTL problems and prevent them from propagating into the physical design, where they are much more difficult and costly to fix. TeraForm gives SoC designers targeting LSI Logic the confidence they need to focus on system-level integration and innovation, rather than logical-to-physical design iteration." For more information visit www.terasystems.com